Currently, circuits are designed using a specific Registered Transfer Level (RTL) language such as VERILOG, SYSTEM VERILOG, VHDL, etc. (Trademarks). Other proprietary RTL languages are also used such as iHDL (Trademarks), Merlin (produced by Intel, the assignee of the present application) or high level modeling languages such as System-C (Trademarks). Thus, using the specific RTL language, a design engineer is able to design, test and verify a Very Large Scale Integrated (VLSI) circuit prior to manufacturing the circuit.
Further, each specific RTL language includes a corresponding simulator allowing the design engineer to simulate a performance of the designed circuit. Accordingly, when a designed logic includes elements produced by different RTL languages (such as one component designed using Verilog and another component using iHDL), a co-simulator is created to handle communications between the different simulators. However, developing a co-simulator may burden the design process.